In a FAB (Fabrication) process, an electronic circuit may be formed by patterning a semiconductor device on a silicon substrate. Since the device formed through the FAB process may be sensitive to impurities, as shown in FIG. 1, passivation 3 may be coated, and may protect the device from external factors.
Passivation 3 may not be coated on an upper metal pad 8 because electrode terminal 5 may be formed on upper metal pad 8. Electrode terminal 5 may be provided to electrically connect upper metal pad 8 to the outside, for example to receive a voltage operating the device of the semiconductor substrate.
Electrode terminal 5 may be formed low in a region in which the passivation is not coated according to a related art pattern step. Consequentially, a dimple phenomenon may be caused. A dimple phenomenon may be where a recess is caused in central portion A of electrode 5.
If the dimple phenomenon is generated in electrode terminal 5, the bonding area between electrode terminal 5 and a packaging module may be reduced in the process of packaging the silicon substrate. This may increase a resistance. To improve the dimple phenomenon, a method for lowering the height of the passivation may be used. However, if the height of the passivation is too low, a gap fill phenomenon of an upper metal may be generated.